Technology Updates

Improved Interconnect Technologies for 3D ICs and 3D Packages

The electronics industry continues to strive towards a common goal – to pack more functionality into smaller form factors. For this, the industry depends on constant reductions in the size of chip of chip packages. Maintaining the tempo predicted by the famous Moore’s Law, the integrated circuit (IC) makers are constantly improving their fabrication processes and designs to fit more components into smaller footprints. However, the electronics industry is not satisfied with even that – they want more!

This has resulted in three – dimensional (3D) ICs and packages. A 3D IC is basically a stack of multiple silicon wafers and dies connected through vertical electrical connections, such as through – silicon vias (TSVs), in a way that they behave like a single device. Wikipedia defines a TSV as a “vertical electrical connection (via) passing completely through a silicon wafer or die.”

A step above, we have 3D packages, that is, interconnected stacks of two or more chips. The stacked chips may be wired together along their edges, but vertical connection using TSVs is now emerging as the more popular option since it does not add to the dimensions of the stack. There are several TSV designs and production technologies in use.

Of course, engineers are never satisfied – even as TSV is gaining popularity, next – generation technologies are already being demonstrated. One such wireless interconnect technology was described by Yasufumi Sugimori at the International Solid – State Circuit Conference 2009. The technology used coupled inductors to send signals between staked die, across a distance of 120 µm. This coupling avoids the need for TSVs, saving the cost of this wafer processing step. According to Sugimori’s estimate, the power spent communicating through the stacked chips will only be half of what is spent in today’s staked chip packages, while the area spent on communication circuits can be reduced 40 times.

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